1. Technical Field
The invention relates to field programmable gate arrays. More particularly, the invention relates to an interconnect architecture for a field programmable gate array.
2. Description of the Prior Art
A conventional field programmable gate array ("FPGA") is a programmable logic device that consists of a matrix of configurable logic elements ("CLEs") embedded in a configurable interconnect mesh. The configuration control of the CLE functions and routing network define the function of the device. The device is referred to as a "field programmable" device because the array of CLEs contained in the device can be configured and interconnected by the user in the user's facility by means of special hardware and software.
FPGAs are well known in the art. For example, R. Freeman, Configurable Electrical Circuit Having Configurable Logic Elements and Configurable Interconnects, U.S. Pat. No. 4,870,302, issued 26 Sep. 1989 describes a configurable logic array that includes a plurality of CLEs variably interconnected in response to control signals to perform a selected logic function, and in which a memory is used to store the particular data used to configure the CLEs. W. Carter, Special Interconnect For Configurable Logic Array, U.S. Pat. No. 4,642,487, issued 10 Feb. 1987 describes a special interconnect circuit for interconnecting CLEs in an FPGA without using the general interconnect structure of the FPGA. W. Carter, Configurable Logic Element, U.S. Pat. No. 4,706,216, issued 10 Nov. 1987 describes a CLE that includes a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic circuit.
A CLE may be electrically programmed by control bits to provide any one of a plurality of logic functions. A CLE may include the circuit elements necessary to provide an AND gate, flip flop, latch, inverter, NOR gate, exclusive OR gate, and certain combinations of these functions, or a CLE may include a look-up table that offers a user all functions of several input signals. The particular function performed by the CLE is determined by control signals that are applied to the CLE from a control logic circuit.
In a field programmable device, the CLE is configured to implement a selected one of its functions without any change in physical structure. In general, a specific set of control signals is transmitted to a specific CLE to control the configuration of that CLE or a set of values is loaded into a look-up table to provide the truth table of the desired function. Control signals are applied to every CLE in the device. The values of the control bits provided to a CLE depend upon the function the CLE is to perform. The configuration of each CLE is therefore determined by the user's intended function of the integrated circuit.
A conventional FPGA comprises a plurality of CLEs, each CLE having input leads and one or more output leads, a general interconnect structure, and a set of programmable interconnection points (PIPs) for connecting the general interconnect structure to each input lead and each output lead. Also, each lead in the general interconnect structure can be connected to one or more other interconnect leads by programming an associated PIP.
The various PIPs in an FPGA are typically programmed by loading memory cells which control the gates of pass transistors or by connecting selected antifuses in an antifuse FPGA. A specific FPGA configuration having a desired function is created by configuring each CLE and forming paths through the interconnect structure within the FPGA to connect the CLEs.
Each PIP in an FPGA is programmed by opening or closing one or more switches associated with the PIP, such that a specified signal path is defined. Such switches may be implemented by applying a control signal to the gate of a pass transistor. Alternatively, if the PIP is part of a multiplexer in which only one of several PIPs will be turned on at one time, several control signals may be decoded to determine which PIP is turned on.
One problem with the known approach to routing signals through an FPGA interconnect structure is caused by using many pass transistors to form a path. Each transistor has an impedance. As a result, several pass transistors connected in series can introduce a significant impedance into a path. Additionally, each interconnect lead and pass transistor introduces a capacitive element that combines with the impedance to produce a propagation delay over the associated path. Delay is especially pronounced if a long path is required because the path may be implemented through several shorter segments and several pass transistors. There is a need for an architecture which avoids the delay of longer paths and offers resource-efficient short paths.
In addition to avoiding long delays, it is desirable to offer predictable delay. The signal path chosen to interconnect one logic element to another logic element is governed by algorithms implemented in software routines. The user may exercise some control over the signal paths chosen by the software, but it is not practical for the user to control all signal paths in a design. The software may choose a large number of different interconnect segment and switch combinations to realize a particular signal path. Since the number of interconnect segments and pass transistors will vary from combination to combination, the delay through the signal path may also vary significantly, depending on the choice made by the software. This variation in delay is undesirable. It would be further advantageous to provide an FPGA interconnect structure that did not have significant delay differences depending upon the signal path realized by the software.